1. Field of the Invention
The present invention relates to bus bandwidth utilization. More particularly, the present invention relates to optimizing bus bandwidth utilization in a high-latency, bursty bus environment by using a prefetch cache to hold data for multiple small-sized data request.
2. Background
In a high bus transaction environment where read accesses range from single word to multiple-word burst accesses it becomes important to optimize memory bus bandwidth utilization. Each read access requires some form of handshaking between a memory bus interface and a device sought to be accessed that are attached to the memory bus, such as a memory controller servicing a memory store. Each read access incurs a bandwidth overhead cost due to handshaking because handshaking consumes bus bandwidth that would have been otherwise available for transmitting access requests from other clients or additional data. Thus, single word accesses are more inefficient than multiple-word burst accesses because less data are transferred for a given bandwidth consumed.
Inefficient single word accesses take away bus time from other clients who may access the bus more efficiently such as clients that can perform large data access per request-grant handshake, further decreasing the memory bus interface's ability to provide optimum utilization of available memory bus bandwidth.
Moreover, in an environment where a memory controller servicing the data access through a memory bus needs to service high latency devices, such as hard drives, so that data may be transferred to another location through a high speed serial bus, such as a fibre channel bus, it becomes even more important that data accesses through the memory bus are performed efficiently.
Accordingly, it would be desirable to handle memory bus access requests of various sizes and without restricting clients to only performing large data fetches, while maintaining optimum utilization of the memory bus bandwidth.